1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material having low permittivity to enhance device performance.
2. Description of the Related Art
In an integrated circuit, a huge number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, filled with an appropriate metal and providing the electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of up to twelve stacked metallization layers that may be employed on sophisticated aluminum-based microprocessors. However, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper is a metal generally considered to be a viable candidate for replacing aluminum due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. Despite these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called damascene technique (single and dual) is therefore preferably used wherein a dielectric layer is first applied and then patterned to receive trenches and vias, which are subsequently filled with copper. A further major drawback of the use of copper is its propensity to readily diffuse in many dielectric materials, such as silicon dioxide, which is a well-established and approved dielectric material in fabricating integrated circuits.
It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. The barrier material provided between the copper and the dielectric material should, however, in addition to the required barrier characteristics, exhibit good adhesion to the dielectric material as well as to the copper to impart superior mechanical stability to the interconnect and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnection.
With the continuous shrinkage of features sizes of the circuit elements, the dimensions of the interconnects are reduced too, thereby also necessitating a reduced layer thick-ness of the barrier materials in interconnects so as to not unduly consume precious space of the actual metal that exhibits a considerably higher conductivity compared to the barrier material. Hence, complex barrier technologies are required to support further device scaling, wherein the usage of dielectric materials with reduced permittivity may even impart further increased constraints to the barrier layer, as will be described with reference to FIGS. 1a-1c for a typical process technique for sophisticated copper-based integrated circuits.
FIG. 1a depicts a schematic cross-sectional view of a semiconductor structure 100 comprising a substrate 101, for example, a semiconductor substrate bearing a plurality of individual circuit elements (not shown), such as transistors, resistors, capacitors and the like. The substrate 101 is representative of any type of appropriate substrate with or without any additional circuit elements and may, in particular, represent sophisticated integrated circuit substrates having included therein circuit elements with critical feature sizes in the deep sub-micron range. A first dielectric layer 102 is formed above the substrate 101 and includes a conductive region 104, for instance an interconnect feature comprised of a metal line 103, such as a copper line, and a first barrier layer 106 comprised of tantalum, and a second barrier layer 105 comprised of tantalum nitride. The dielectric layer 102 and the interconnect feature 104 may represent a first metallization layer. An etch stop layer 110 comprised of, for instance, silicon nitride, nitrogen-enriched silicon carbide and the like, is formed above the dielectric layer 102 and partially above the copper line 103. A second dielectric layer 107 comprised of a dielectric material including at least a material of low permittivity, as is typically used for obtaining reduced parasitic capacitances between adjacent metal lines, is formed over the etch stop layer 110 and the first dielectric layer 102 and has formed therein a trench 109 and a via 108 connecting to the metal line 103, thereby exposing a contamination layer 111 located on a surface portion 103a of the copper line 103. For example, the dielectric layer 107 may be comprised of fluorine-doped silicon dioxide deposited from TEOS, which is also referred to as FTEOS, and which has a lower permittivity compared to pure TEOS silicon dioxide. In other approaches, the dielectric layer 107 may include a first sub-layer 107a comprised of FTEOS silicon dioxide and a second dielectric layer 107b comprised of a so-called low-k material, as the parasitic capacitances between laterally adjacent metal lines are more critical than between vias and vertically adjacent metal lines.
A typical process flow for forming the semiconductor structure 100 as shown in FIG. 1a may include the following steps, wherein, for the sake of simplicity, only the formation of the second metallization layer, i.e., the second dielectric layer 107 and the metal interconnect feature to be formed therein, will be described in detail as the processes in forming the interconnect feature 104 in the first dielectric layer 102 may substantially involve the same process steps. Thus, after planarizing the dielectric layer 102, including the interconnect feature 104, and forming the etch stop layer 110, thereby passivating the interconnect feature 104, as pure copper forms a highly reactive surface, the dielectric layer 107 is deposited by well-known deposition methods, such as plasma enhanced chemical vapor deposition (PECVD), spin-on techniques and the like, wherein, as previously pointed out, silicon dioxide including fluorine deposited from TEOS by chemical vapor deposition is frequently employed. Subsequently, the dielectric layer 107 is patterned by well-known photolithography and anisotropic etch techniques, wherein an intermediate etch stop layer (not shown) may be used in patterning the trench 109.
It should further be noted that different approaches may be employed in forming the trench 109 and the via 108, such as a so-called via first trench last approach, or a trench first via last approach, wherein, in the former approach, the via 108 may be filled with metal prior to the formation of the trench 109. In the present example, a so-called dual damascene technique is described in which the trench 109 and the via 108 are simultaneously filled with metal. Irrespective of the etch scheme used, in the last etch step, the etch stop layer 110 is opened and the copper surface 103a is exposed to the reactive etch ambient, which may contain fluorine, in particular when the dielectric layer 107 also comprises fluorine. As a consequence, the contamination layer 111 containing a copper/fluorine/oxygen compound is formed on the surface portion 103a. Since the contamination layer 111 may significantly affect the further processes, such as the formation of a barrier layer and seed layer for the subsequent copper fill process, thereby reducing via reliability and lowering product yield and reliability, the contamination layer 111 may be removed by a wet chemical etch process on the basis of, for example, diluted fluoric acid (HF). It has been found that during this wet chemical process, the contamination layer 111 is effectively removed yet the surface portion 103a is again exposed to a reactive environment, thereby resulting in a recreation of a contamination layer having a similar negative effect on the further processing as the layer 111. Consequently, during the process of forming a barrier/adhesion layer, a sputter pre-clean process is performed for removing contaminants from the surface portion 103a. 
FIG. 1b schematically shows the semiconductor structure 100 during an initial phase of a sputter process, indicated as 112, wherein argon ions may be directed to the surface portion 103a in an attempt to remove the contamination layer 111 or contaminants 111a that are still left after the wet chemical clean process that may optionally be performed. Thereafter, the sputter parameters are adjusted to deposit a barrier/adhesion layer, for instance on the basis of tantalum and/or tantalum nitride. Owing to the incomplete removal of the contaminants 111a during the initial pre-clean process, irregularities may still be present at the surface portion 103a after the formation of the barrier/adhesion layer, the formation of a seed layer and the deposition of the bulk copper.
FIG. 1c schematically shows the semiconductor structure 100 with a barrier/adhesion layer 113 and a copper seed layer 114 formed on the structure 100 and within the trench 109 and the via 108. At the surface portion 103a, irregularities 111b may be formed, which may lead to a reduced via reliability due to, for instance, an increased transition resistivity between the via 108, after being filled with copper, and the metal line 103. The problem of reduced via reliability is even exacerbated for highly scaled devices, since the reduced cross-section of the via 108 may require even more restricted margins with respect to resistivity fluctuations of the vias 108.
In view of the above-identified problems, there is a need for an improved technique allowing the formation of more reliable metal interconnects, especially of copper inter-connects, in highly scaled semiconductor devices.